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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad14060/AD14060L one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 quad-sharc ? dsp multiprocessor family functional block diagram performance features adsp-21060 core processor ( ... 3 4) 480 mflops peak, 320 mflops sustained 25 ns instruction rate, single-cycle instruction executionCeach of four processors 16 mbit shared sram (internal to sharcs) 4 gigawords addressable off-module memory twelve 40 mbyte/s link ports (three per sharc) four 40 mbit/s independent serial ports (one from each sharc) one 40 mbit/s common serial port 5 v and 3.3 v operation 32-bit single precision and 40-bit extended precision ieee floating point data formats, or 32-bit fixed point data format ieee jtag standard 1149.1 test access port and on-chip emulation packaging features 308-lead ceramic quad flatpack (cqfp) 2.05" (52 mm) body size cavity up or down, configurable low profile, 0.160" height hermetic 25 mil (0.65 mm) lead pitch 29 grams (typical) u jc = 0.36 8 c/w general description the ad14060/AD14060L quad-sharc is the first in a family of high performance dsp multiprocessor modules. the core of the multiprocessor is the adsp-21060 dsp microcomputer. the ad14060/AD14060L modules have the highest perfor- mance density and lowest costperformance ratios of any in their class. they are ideal for applications requiring higher levels of performance and/or functionality per unit area. the ad14060/AD14060L takes advantage of the built-in multi- processing features of the adsp-21060 to achieve 480 peak mflops with a single chip type, in a single package. the on- chip sram of the dsps provides 16 mbits of on-module shared sram. the complete shared bus (48 data, 32 address) is also brought off-module for interfacing with expansion memory or other peripherals. sharc is a registered trademark of analog devices, inc. the adsp-21060 link ports are interconnected to provide direct communication among the four sharcs as well as high speed off-module access. internally, each sharc has a direct link port connection. externally, each sharc has a total of 120 mbytes/s link port bandwidth. multiprocessor performance is enhanced with embedded power and ground planes, matched impedance interconnect, and opti- mized signal routing lengths and separation. the fully tested and ready-to-insert multiprocessor also significantly reduces board space. cpa sport 1 tdi eboot, lboot, bms cs timexp link 1 link 3 link 4 irq 2-0 flag 2,0 emu clkin reset sport 0 tck, tms, trst flag 1 flag 3 sharc_a (id 2-0 = 1) cpa sport 1 eboot, lboot, bms cs timexp link 1 link 3 link 4 irq 2-0 flag 2,0 emu clkin reset sport 0 tck, tms, trst flag 1 flag 3 tdo sharc_b (id 2-0 = 2) link 0 link 2 link 5 tdi link 0 link 2 link 5 tdo eboot, lboot, bms emu clkin reset sport 0 tck, tms, trst flag 1 flag 3 link 0 link 2 link 5 tdo link 0 link 2 link 5 tdi eboot, lboot, bms emu clkin reset sport 0 tck, tms, trst flag 1 flag 3 tdi sharc bus ( addr 31-0 , data 47-0 , ms 3-0 , rd, wr, page, adrclk, sw, ack, sbts, hbr, hbg, redy, br 6-1 , rpba, dmar 1.2 , dmag 1.2 ) cpa sport 1 tdo cs timexp link 1 link 3 link 4 irq 2-0 flag 2,0 cpa sport 1 sharc_d (id 2-0 = 4) sharc_c (id 2-0 = 3) cs timexp link 1 link 3 link 4 irq 2-0 flag 2,0 ad14060/ AD14060L
ad14060/AD14060L C2C rev. a detailed description architectural features adsp-21060 core the ad14060/AD14060L is based on the powerful adsp-21060 (sharc) dsp chip. the adsp-21060 sharc combines a high performance floating-point dsp core with integrated, on- chip system features including a 4 mbit sram memory, host processor interface, dma controller, serial ports, and both link port and parallel bus connectivity for glueless dsp multiprocess- ing, (see figure 1). it is fabricated in a high speed, low power cmos process, and has a 25 ns instruction cycle time. the arith- metic/ logic unit (alu), multiplier and shifter all perform single- cycle instructions, and the three units are arranged in parallel, maximizing computational throughput. the sharc features an enhanced harvard architecture in which the data memory (dm) bus transfers data, and the pro- gram memory (pm) bus transfers both instructions and data. there is also an on-chip instruction cache which selectively caches only those instructions whose fetches conflict with the pm bus data accesses. this combines with the separate program and data memory buses to enable three-bus operation for fetch- ing an instruction and two operands, all in a single cycle. the sharc also contains a general purpose data register file, which is a 10-port, 32-register (16 primary, 16 secondary) file. each sharcs core also implements two data address generators (dags), implementing circular data buffers in hard ware. the dags contain sufficient registers to allow the creation of up to 32 circular buffers. the 48-bit instruction word accom modates a variety of parallel operations, for concise programming. for ex- ample, the adsp-21060 can conditionally execute a multi ply, an add, a subtract, and a branch, all in a single instruction. the sharcs contain 4 mbits of on-chip sram each, orga- nized as two blocks of 2 mbits, which can be configured for different combinations of code and data storage. the memory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 80k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 4 megabits. a 16-bit floating-point storage format is supported which effectively doubles the amount of data that may be stored on chip. conversion between the 32-bit floating point and 16- bit floating point formats is done in a single instruction. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor or dma con- troller. the dual-ported memory and separate on-chip buses allow two data transfers from the core and one from i/o, all in a single cycle. shared memory multiprocessing the ad14060/AD14060L takes advantage of the powerful multiprocessing features built into the sharc. the sharcs are connected to maximize the performance of this cluster-of-four architecture, and still allow for off-module expansion. the ad14060/AD14060L in itself is a complete shared memory multiprocessing system, as shown in figure 3. the unified ad- dress space of the sharcs allows direct interprocessor ac- cesses of each sharcs internal mem ory. in other words, each sharc can directly access the internal memory and iop registers of each of the other sharcs by simply reading or writing to the appropriate address in multiprocessor memory space (see figure 2)this is called a direct read or direct write . serial ports (2) link ports (6) 4 6 6 36 iop registers ( memory mapped) control, status, and data buffers i/o processor timer instruction cache 32 x 48-bit addr data data data addr addr data addr two independent dual-ported blocks processor port i/o port block 0 block 1 jtag test and emulation 7 host port addr bus mux ioa 17 iod 48 multiprocessor interface dual-ported sram external port data bus mux 48 32 24 pm address bus dm address bus pm data bus dm data bus bus connect (px) data register file 16 x 40-bit barrel shifter alu multiplier dag1 8 x 4 x 32 32 48 40/32 core processor dma controller program sequencer dag2 8 x 4 x 24 figure 1. adsp-21060 processor block diagram (core of the ad14060)
ad14060/AD14060L C3C rev. a iop registers normal word addressing 0x0000 0000 0x0002 0000 0x0004 0000 0x0008 0000 0x0010 0000 0x0018 0000 0x0020 0000 0x0028 0000 0x0030 0000 0x0038 0000 0x003f ffff short word addressing internal memory space of sharc_b id=010 internal memory space of sharc_a id=001 internal memory space of sharc_c id=011 internal memory space of sharc_d id=100 internal memory space of adsp-2106x with id=101 internal memory space of adsp-2106x with id=110 broadcast write to all adsp-2106xs normal word addressing: 32-bit data words 48-bit instruction words short word addressing: 16-bit data words ms 0 bank 0 0x0040 0000 0xffff ffff multiprocessor memory space bank 1 bank 2 dram (optional) bank 3 nonbanked ms 1 ms 2 ms 3 bank size is selected by msize bit field of syscon register. external memory space internal memory space (individual sharcs) internal to ad14060 external to ad14060 figure 2. ad14060/AD14060L memory map clkin reset rpba cpa bootselect a bootselect bcd dmar1,2 dmag1,2 sport0 flag1 jtag 1x clock links 1, 3, & 4; irq 2-0 ; flags 2 & 0; timexp, sport1 sharc_d links 1, 3, & 4; irq 2-0 ; flags 2 & 0; timexp, sport1 sharc_c rd wr ack ms 3-0 page sbts sw adrclk cs hbr hbg redy br 1-6 data 47-0 addr 31-0 sharc_a links 1, 3, & 4; irq 2-0 ; flags 2 & 0; timexp, sport1 sharc_b links 1, 3, & 4; irq 2-0 ; flags 2 & 0; timexp, sport1 ad14060/AD14060L (quad processor cluster) system expansion figure 3. complete shared memory multiprocessing system
ad14060/AD14060L C4C rev. a bus arbitration is accomplished with the on-sharc arbitration logic. each sharc has a unique id, and drives the bus-request (br) line corresponding to its id, while monitoring all others. br 1C br 4 are used within the ad14060/AD14060L, while br 5 and br 6 can be used for expansion. all bus requests ( br 1C br 6) are included in the module i/o. two different priority schemes, fixed and rotating, are available to resolve competing bus requests. the rpba pin selects which scheme is used: when rpba is high, rotating priority bus arbitra- tion is selected, and when rpba is low, fixed priority is selected. table i. rotating priority arbitration example hardware processor ids cycle id1 id2 id3 id4 id5 id6 1m12 br345 initial priority assignments 2 4 5 br m-br 1 2 3 3 4 5 br m 1 2 3 4 5 br m 1 2 3 4 br 51 br23 45m final priority assignments notes 1C5 = assigned priority. m = bus mastership (in that cycle). br = requesting bus mastership with brx. bus mastership is passed from one sharc to another during a bus transition cycle . a bus transition cycle only occurs when the current bus master deasserts its br line and one of the slave sharcs asserts its br line. the bus master can therefore re- tain bus mastership by keeping its br line asserted. when the bus master deasserts its br line, and no other br line is as- serted, then the master will not lose any bus cycles. when more than one sharc asserts its br line, the sharc with the highest priority request becomes bus master on the following cycle. each sharc observes all of the br lines, and therefore tracks when a bus transition cycle has occurred, and which processor has become the new bus master. master processor changeover incurs only one cycle of overhead. an example bus transition sequence is shown in table i. bus locking is possible, allowing indivisible read-modify-write sequences for semaphores. in either the fixed or rotating priority scheme, it is also possible to limit the number of cycles the master can control the bus. the ad14060/AD14060L also provides the option of using the core priority access (cpa) mode of the sharc. using the cpa signal allows external bus accesses by the core processor of a slave sharc to take priority over ongoing dma transfers. also, each sharc can broadcast write to all other sharcs simultaneously, allowing the imple- mentation of reflective semaphores. the bus master can communicate with slave sharcs by writ- ing messages to their internal iop registers. the msrg0C msrg7 registers are general-purpose registers that can be used for convenient message passing, semaphores and resource shar- ing between the sharcs. for message passing, the master communicates with a slave by writing and/or reading any of the eight message registers on the slave. for vector interrupts, the master can issue a vector interrupt to a slave by writing the address of an interrupt service routine to the slaves virpt register. this causes an immediate high priority interrupt on the slave which, when serviced, will cause it to branch to the speci- fied service routine. off-module memory and peripherals interface the ad14060/AD14060Ls external port provides the interface to off-module memory and peripherals (see figure 5). this port consists of the complete external port bus of the sharc, bused together in common among the four sharcs. the 4-gigaword off-module address space is included in the adsp-14060s unified address space. addressing of external memory devices is facilitated by each sharc internally de- coding the high order address lines to generate memory bank select signals. separate control lines are also generated for sim- plified addressing of page-mode dram. the ad14060/ AD14060L also supports programmable memory wait states and external memory acknowledge controls to allow interfacing to dram and peripherals with variable access, hold and disable time requirements. link port i/o each individual sharc features six 4-bit link ports that facili- tate sharc-to-sharc communication and external i/o inter- facing. each link port can be configured for either 1 or 2 operation, allowing each to transfer either 4 or 8 bits per cycle. the link ports can operate independently and simultaneously, with a maximum bandwidth of 40 mbytes/s each, or a total of 240 mbytes/s per sharc. the ad14060/AD14060L optimizes the link port connections internally, and brings a total of twelve of the link ports off-mod- ule for user-defined system connections. internally, each sharc has a connection to the other three sharcs with a dedicated link port interface. thus, each sharc can directly interface with its nearest and next-nearest neighbor. the remaining three link ports from each sharc are brought out independently from each sharc. a maximum of 480 mbytes/s link port bandwidth is then available off of the ad14060/AD14060L. the link port connections are detailed in figure 4. sharc_a sharc_b sharc_d sharc_c 1 3 4 1 3 4 1 3 4 1 3 4 55 55 22 22 0 0 0 0 figure 4. link port connections link port 4, the boot link port, is brought off independently from each sharc. individual booting is then allowed, or chained link port booting is possible as described under link port booting. link port data is packed into 32-bit or 48-bit words, and can be directly read by the sharc core processor or dma- transferred to on-sharc memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive.
ad14060/AD14060L C5C rev. a addr 31C0 data 47C0 cpa br 2C6 br 1 bms control ad14060/ AD14060L 5 1x clock reset addr data host processor interface (optional) ack cs global memory and peripherals (optional) oe we addr data cs addr data boot eprom (optional) rd wr ms 3C0 sbts sw adrclk cs hbr hbg redy ack reset rpba clkin page cpa br 1C5 br 6 control adsp-2106x #6 (optional) addr 31C0 data 47C0 5 reset rpba clkin addr 31C0 data 47C0 cpa br 1, 2, 3, 4, 6 br 5 control adsp-2106x #5 (optional) 5 3 id 2C0 3 id 2C0 reset rpba clkin serials links discretes 101 110 figure 5. optional system interconnections
ad14060/AD14060L C6C rev. a serial ports the sharc serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. each sharc has two serial ports. the ad14060/AD14060L provides direct access to serial port 1 of each sharc. serial port 0 is bused together in common to each sharc, and brought off-module. the serial ports can operate at the full clock rate of the module, providing each with a maximum data rate of 40 mbit/s. inde- pendent transmit and receive functions provide more flexible communications. serial port data can be automatically trans- ferred to and from on-sharc memory via dma, and each of the serial ports offers time division multiplexed (tdm) multi- channel mode. the serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional m -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. program booting the ad14060/AD14060L supports automatic downloading of programs following power-up or a software reset. the sharc offers four options for program booting: 1) from an 8-bit eprom; 2) from a host processor; 3) through the link ports; and 4) no-boot. in no-boot mode, the sharc starts executing instructions from address 0x0040 0004 in external memory. the boot mode is selected by the state of the following signals: bms, eboot, and lboot. on the ad14060/AD14060L, sharc_as boot mode is sepa- rately controlled, while sharcs b, c, and d are controlled as a group. with this flexibility, the ad14060/AD14060L can be configured to boot in any of the following methods. multiprocessor host booting to boot multiple adsp-21060 processors from a host, each adsp-21060 must have its eboot, lboot and bms pins configured for host booting: eboot = 0, lboot = 0, and bms = 1. after system power-up, each adsp-21060 will be in the idle state and the br x bus request lines will be deasserted. the host must assert the hbr input and boot each adsp-21060 by asserting its cs pin and downloading instructions. multiprocessor eprom booting there are two methods of booting the multiprocessor system from an eprom. sharc_a is booted, which then boots the others. the eboot pin on the sharc_a must be set high for eprom booting. all other adsp-21060s should be configured for host booting (eboot = 0, lboot = 0, and bms = 1), which leaves them in the idle state at start-up and allows sharc_a to become bus master and boot itself. only the bms pin of sharc_a is connected to the chip select of the eprom. when sharc_a has finished booting, it can boot the re- maining adsp-21060s by writing to their external port dma buffer 0 (epb0) via multiprocessor memory space. all adsp-21060s boot in turn from a single eprom. the bms signals from each adsp-21060 may be wire-ored together to drive the chip select pin of the eprom. each adsp-21060 can boot in turn, according to its priority. when the last one has finished booting, it must inform the others (which may be in the idle state) that program execution can begin. multiprocessor link port booting booting can also be accomplished from a single source through the link ports. link buffer 4 must always be used for booting. to simultaneously boot all of the adsp-21060s, a parallel common connection is available through link port 4 on each of the processors. or, using the daisy chain connection that exists between the processors link ports, each adsp-21060 can boot the next one in turn. in this case, the link assignment register (lar) must be programmed to configure the internal link ports with link buffer 4. multiprocessor booting from external memory if external memory contains a program after reset, then sharc_a should be set up for no boot mode; it will begin ex- ecuting from address 0x0040 0004 in external memory. when booting has completed, the other adsp-21060s may be booted by sharc_a if they are set up for host booting, or they can begin executing out of external memory if they are set up for no boot mode. multiprocessor bus arbitration will allow this booting to occur in an orderly manner. host processor interface the ad14060/AD14060Ls host interface allows for easy con- nection to standard microprocessor buses, both 16-bit and 32- bit, with little additional hardware required. asynchronous transfers at speeds up to the full clock rate of the module are supported. the host interface is accessed through the ad14060/ AD14060L external port and is memory-mapped into the uni- fied address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the ad14060/AD14060Ls external bus with the host bus request ( hbr ), host bus grant ( hbg ), and ready (redy) signals. the host can directly read and write the internal memory of the sharcs, and can access the dma channel setup and mailbox registers. vector interrupt support is provided for efficient execution of host commands. direct memory access (dma) controller the sharcs on-chip dma control logic allows zero-over head data transfers without processor intervention. the dma con- troller operates independently and invisibly to each sharcs processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between sharc internal memory and either external memory, external peripherals, or a host processor. dma transfers can also occur between the sharcs internal memory and its serial ports or link ports. dma trans- fers between external memory and external peripheral devices are another option. external bus packing to 16-, 32- or 48-bit words is performed during dma transfers. ten channels of dma are available on the sharcstwo via the link ports, four via the serial ports, and four via the processors external port (for either host processor, other sharcs, memory, or i/o transfers). four additional link port dma channels are shared with serial port 1 and the external port. programs can be downloaded to the sharcs using dma transfers. asynchronous off-module peripherals can control two dma channels using dma request/grant lines ( dmar1-2 , dmag1-2 ). other dma features include interrupt generation upon completion of dma transfers and dma chaining for automatic linked dma transfers.
ad14060/AD14060L C7C rev. a development tools the adsp-14060 is supported with a complete set of software and hardware development tools, including an ez-lab ? in- circuit emulator, and development software. analog devices adsp-21000 family development software includes an easy to use assembler based on an algebraic syntax, an assembly library/librarian, a linker, an instruction-level simulator, an ansi c optimizing compiler, the cbug? c source-level debugger, and a c runtime library including dsp and mathematical functions. the optimizing compiler includes numerical c extensions based on the work of the ansi numerical c extensions group. numerical c provides exten- sions to the c language for array selection, vector math op- erations, complex data types, circular pointers and variably dimensioned arrays. the adsp-21000 family development software is available for both the pc and sun platforms. the sharc ez-kit combines the adsp-21000 family de- velopment software for the pc and the ez-lab development board in one package. the adsp-2106x ez-ice ? emulator uses the ieee 1149.1 jtag test access port of the adsp-2106x processor to monitor and control the target board processor during emulation. the ez-ice provides full-speed emulation, allowing inspection and modification of memory, registers and processor stacks. nonintrusive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator does not affect target system loading or timing. further details and ordering information are available in the adsp-21000 family hardware & software development tools data sheet (adds-2100xx-tools). this data sheet can be requested from any analog devices sales office or distributor, or from the literature center. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc pc plug-in cards, multiprocessor sharc vme boards, and daughter card modules with multiple sharcs and additional memory. these modules are based on the sharcpac module specification. third party software tools include an ada compiler, dsp libraries, operating systems and block diagram design tools. quad-sharc development board the blacktip-mcm, ad14060 development board and soft- ware, is available from bittware research systems, inc. this board has one ad14060 bitsi interface, prom and sram expansion options on an isa card. it is supported by bittwares sharc software development package. bittware can be con- tacted at 1-800-848-0436. other package details the ad14060/AD14060L contains 16 on-module 0.018 micro- farad bypass capacitors. it is recommended that in the target system at least four additional capacitors, of 0.018 microfarad value, be placed around the moduleone near each of the four corners. the top surface, lid, of the ad14060/AD14060L is electrically connected to gnd on the industrial and military grade parts. additional information this data sheet provides a general overview of the ad14060/ AD14060L architecture and functionality. for detailed infor- mation on the adsp-2106x sharc and the adsp-21000 family core architecture and instruction set, refer to the adsp- 2106x sharc users manual. ez-ice and ez-lab are registered trademarks of analog devices, inc. cbug is a trademark of analog devices, inc.
ad14060/AD14060L C8C rev. a pin type function addr 31-0 i/o/t external bus address. (common to all sharcs) the ad14060/AD14060L outputs addresses for external memory and peripherals on these pins. in a multiprocessor system, the bus master outputs addresses for read/writes on the internal memory or iop registers of slave adsp-2106xs. the ad14060/ AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing the internal memory or iop registers of internal adsp-21060s. data 47-0 i/o/t external bus data . (common to all sharcs) the ad14060/AD14060L inputs and outputs data and instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans- ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47- 8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. in prom boot mode, 8-bit data is transferred over bits 23-16. pull-up resistors on unused data pins are not necessary. ms 3-0 o/t memory select lines. (common to all sharcs) these lines are asserted (low) as chip selects for the corresponding banks of external memory. memory bank size must be defined in the individual adsp- 21060s system control registers (syscon). the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. ms 0 can be used with the page signal to implement a bank of dram memory (bank 0). in a multiprocessing system, the ms 3-0 lines are output by the bus master. rd i/o/t memory read strobe. (common to all sharcs) this pin is asserted (low) when the ad14060/ AD14060L reads from external devices or when the internal memory of internal adsp-2106xs is being accessed. external devices (including other adsp-2106xs) must assert rd to read from the ad14060/ AD14060Ls internal memory. in a multiprocessing system, rd is output by the bus master and is input by all other adsp-2106xs. wr i/o/t memory write strobe. (common to all sharcs) this pin is asserted (low) when the ad14060/ AD14060L writes to external devices or when the internal memory of internal adsp-2106xs is being ac- cessed. external devices (including other adsp-2106xs) must assert wr to write to the ad14060/ AD14060Ls internal memory. in a multiprocessing system wr is output by the bus master and is input by all other adsp-2106xs. page o/t dram page boundary. (common to all sharcs) the ad14060/AD14060L asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the indi- vidual adsp-21060s memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system, page is output by the bus master. adrclk o/t clock output reference. (common to all sharcs) in a multiprocessing system, adrclk is output by the bus master. sw i/o/t synchronous write select. (common to all sharcs) this signal is used to interface the ad14060/ AD14060L to synchronous memory devices (including other adsp-2106xs). the ad14060/AD14060L asserts sw (low) to provide an early indication of an impending write cycle, which can be aborted if wr is not later asserted (e.g., in a conditional write instruction). in a multiprocessing system, sw is output by the bus master and is input by all other adsp-2106xs to determine if the multiprocessor memory access is a read or write. sw is asserted at the same time as the address output. a host processor using synchronous writes must assert this pin when writing to the ad14060/AD14060L. ack i/o/s memory acknowledge. (common to all sharcs) external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other pe- ripherals to hold off completion of an external memory access. the ad14060/AD14060L deasserts ack, as an output, to add wait states to a synchronous access of its internal memory. in a multiprocess- ing system, a slave adsp-2106x deasserts the bus masters ack input to add wait state(s) to an access of its internal memory. the bus master has a keeper latch on its ack pin that maintains the input at the level it was last driven to. pin function descriptions ad14060/AD14060L pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to v dd or gnd, except for addr 31-0 , data 47-0 , flag 2-0 , sw , and inputs that have internal pull-up or pull-down resistors (cpa, ack, dtx, drx, tclkx, rclkx, lxdat 3-0 , lxclk, lxack, tms and tdi)these pins can be left floating. these pins have a logic- level hold circuit that prevents the input from floating internally. i = input p = power supply (a/d) = active drive o = output s = synchronous (o/d) = open drain g = ground a = asynchronous t = three-state (when sbts is asserted, or when the ad14060/ AD14060L is a bus slave)
ad14060/AD14060L C9C rev. a pin type function sbts i/s suspend bus three-state. (common to all sharcs) external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. if the ad14060/AD14060L attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor/ad14060/AD14060L deadlock, or used with a dram controller. hbr i/a host bus request. (common to all sharcs) must be asserted by a host processor to request control of the ad14060/AD14060Ls external bus. when hbr is asserted in a multiprocessing system, the adsp-2106x that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-2106x places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-2106x bus requests ( br 6-1 ) in a multiprocessing system. hbg i/o host bus grant. (common to all sharcs) acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the ad14060/AD14060L until hbr is released. in a multiprocessing system, hbg is output by the adsp-2106x bus master and is monitored by all others. csa i/a chip select. asserted by host processor to select sharc_a. csb i/a chip select. asserted by host processor to select sharc_b. csc i/a chip select. asserted by host processor to select sharc_c. csd i/a chip select. asserted by host processor to select sharc_d. redy (o/d) o host bus acknowledge. (common to all sharcs) the ad14060/AD14060L deasserts redy (low) to add wait states to an asynchronous access of its internal memory or iop registers by a host. open drain output (o/d) by default; can be programmed in adredy bit of syscon register of individual adsp- 21060s to be active drive (a/d). redy will only be output if the cs and hbr inputs are asserted. br 6-1 i/o/s multiprocessing bus requests. (common to all sharcs) used by multiprocessing adsp-2106xs to arbitrate for bus mastership. an adsp-2106x only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-2106xs, the unused br x pins should be pulled high; br 4-1 must not be pulled high or low because they are outputs. rpba i/s rotating priority bus arbitration select. (common to all sharcs) when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection that must be set to the same value on every adsp-2106x. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-2106x. cpa y (o/d) i/o core priority access. (y = sharc_a, b, c, d) asserting its cpa pin allows the core processor of an adsp-2106x bus slave to interrupt background dma transfers and gain access to the external bus. cpa is an open drain output that is connected to all adsp-2106x in the system if this function is required. the cpa pin of each internal adsp-21060 is brought out individually. the cpa pin has an internal 5 k w pull-up resistor. if core access priority is not required in a system, the cpa pin should be left unconnected. dt0 o/t data transmit (common serial ports 0 to all sharcs, tdm). dt pin has a 50 k w internal pull-up resistor. dr0 i data receive (common serial ports 0 to all sharcs, tdm). dr pin has a 50 k w internal pull-up resistor. tclk0 i/o transmit clock (common serial ports 0 to all sharcs, tdm). tclk pin has a 50 k w internal pull-up resistor. rclk0 i/o receive clock (common serial ports 0 to all sharcs, tdm). rclk pin has a 50 k w internal pull-up resistor. tfs0 i/o transmit frame sync (common serial ports 0 to all sharcs, tdm). rfs0 i/o receive frame sync (common serial ports 0 to all sharcs, tdm). dty1 o/t data transmit (serial port 1 individual from sharc_a, sharc_b, sharc _c, sharc_d) dt pin has a 50 k w internal pull-up resistor. dry1 i data receive (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d) dr pin has a 50 k w internal pull-up resistor.
ad14060/AD14060L C10C rev. a pin type function tclky1 i/o transmit clock (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d) tclk pin has a 50 k w internal pull-up resistor. rclky1 i/o receive clock (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d) rclk pin has a 50 k w internal pull-up resistor. tfsy1 i/o transmit frame sync (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d) rfsy1 i/o receive frame sync (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d) flagy0 i/o/a flag pins. (flag0 individual from sharc_a, sharc_b, sharc_c, sharc_d) each is config- ured via control bits as either an input or output. as an input, it can be tested as a condition. as an out- put, it can be used to signal external peripherals. flag1 i/o/a flag pins. (flag1 common to all sharcs) configured via control bits internal to individual adsp- 21060s as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. flagy2 i/o/a flag pins. (flag2 individual from sharc_a, sharc_b, sharc_c, sharc_d) each is config- ured via control bits as either an input or output. as an input, it can be tested as a condition. as an out- put, it can be used to signal external peripherals. irq y2-0 i/a interrupt request lines. (individual irq 2-0 from y = sharc_a, sharc_b, sharc_c, sharc_d) may be either edge-triggered or level-sensitive. dmar1 i/a dma request 1 (dma channel 7). common to sharc_a, sharc_b, sharc_c, sharc_d. dmar2 i/a dma request 2 (dma channel 8). common to sharc_a, sharc_b, sharc_c, sharc_d. dmag1 o/t dma grant 1 (dma channel 7). common to sharc_a, sharc_b, sharc_c, sharc_d. dmag2 o/t dma grant 2 (dma channel 8). common to sharc_a, sharc_b, sharc_c, sharc_d. lyxclk i/o link port clock (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 1 . each lyxclk pin has a 50 k w internal pull-down resistor which is enabled or disabled by the lpdrd bit of the lcom register, of the adsp-20160. lyxdat3-0 i/o link port data (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 1 . each lyxdat pin has a 50 k w internal pull-down resistor which is enabled or disabled by the lpdrd bit of the lcom register, of the adsp-21060. lyxack i/o link port acknowledge (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 1 . each lyxack pin has a 50 k w internal pull-down resistor which is enabled or disabled by the lpdrd bit of the lcom register, of the adsp-21060. eboota i eprom boot select. (sharc_a) when eboota is high, sharc_a is configured for booting from an 8-bit eprom. when eboota is low, the lboota and bmsa inputs determine booting mode for sharc_a. see the following table. this signal is a system configuration selection which should be hardwired. lboota i link boot. when lboota is high, sharc_a is configured for link port booting. when lboota is low, sharc_a is configured for host processor booting or no booting. see the following table. this signal is a system configuration selection which should be hardwired. bmsa i/o/t 2 boot memory select. output: used as chip select for boot eprom devices (when eboota = 1, lboota = 0). in a multiprocessor system, bms is output by the bus master. input: when low, indicates that no booting will occur and that sharc_a will begin executing instructions from external memory. see the following table. this input is a system configuration selection which should be hardwired. ebootbcd i eprom boot select. (common to sharc_b, sharc_c, sharc_d) when ebootbcd is high, sharc_b, c, d are configured for booting from an 8-bit eprom. when ebootbcd is low, the lbootbcd and bmsbcd inputs determine booting mode for sharc_b, c and d. see the following table. this signal is a system configuration selection which should be hardwired. lbootbcd i link boot. (common to sharc_b, sharc_c, sharc_d) when lbootbcd is high, sharc_b, c, d are configured for link port booting. when lbootbcd is low, sharc_b, c, d are configured for host processor booting or no booting. see the following table. this signal is a system configuration selec- tion which should be hardwired.
ad14060/AD14060L C11C rev. a pin type function bmsbcd i/o/t 2 boot memory select. output: used as chip select for boot eprom devices (when ebootbcd = 1, lbootbcd = 0). in a multiprocessor system, bms is output by the bus master. input: when low, indicates that no booting will occur and that sharc_b, c, d will begin executing instructions from external memory. see table below. this input is a system configuration selection which should be hardwired. eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select) 0 0 1 (input) host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 0 1 0 (input) reserved 1 1 x (input) reserved timexpy o timer expired. (individual timexp from y = sharc_a, sharc_b, sharc_c, sharc_d) asserted for four cycles when the timer is enabled and tcount decrements to zero. clkin i clock in. (common to all sharcs) external clock input to the ad14060/AD14060L. the instruction cycle rate is equal to clkin. clkin may not be halted, changed, or operated below the minimum specified frequency. reset i/a module reset. (common to all sharcs) resets the ad14060/AD14060L to a known state. this input must be asserted (low) at power-up. tck i test clock (jtag). (common to all sharcs) provides an asynchronous clock for jtag boundary scan. tms i/s test mode select (jtag). (common to all sharcs) used to control the test state machine. tms has a 20 k w internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic chain starting at sharc_a. tdi has a 20 k w internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan chain path, from sharc_d. trst i/a test reset (jtag). (common to all sharcs) resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the ad14060/AD14060L. trst has a 20 k w internal pull-up resistor. emu (o/d) o emulation status. (common to all sharcs) must be connected to the adsp-2106x ez-ice target board connector only . v dd p power supply. nominally +5.0 v dc for 5 v devices or +3.3 v dc for 3.3 v devices (26 pins). gnd g power supply return. (28 pins). notes flag3 is connected internally, common to sharc_a, b, c, and d. id pins are hardwired internally as depicted in the block diagram. 1 link ports 0, 2 and 5 are connected internally as described earlier in link port i/o. 2 three-statable only in eprom boot mode (when bms is an output).
ad14060/AD14060L C12C rev. a target board connector for ez-ice probe the adsp-2106x ez-ice emulator uses the ieee 1149.1 jtag test acc ess port of the adsp-2106x to monitor and control the target board processor during emulation. the ez-ice probe requires that the ad14060/AD14060Ls clkin (optional), tms, tck, trst , tdi, tdo, emu and gnd signals be made accessible on the target system via a 14-pin connector (a pin strip header) such as that shown in figure 6. the ez-ice probe plugs directly onto this connector for chip-on-board emu- lation. you must add this connector to your target board design if you intend to use the adsp-2106x ez-ice. the length of the traces between the connector and the ad14060/ AD14060Ls jtag pins should be as short as possible. top view 13 14 11 12 9 10 9 7 8 5 6 3 4 1 2 emu clkin (optional) tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 6. target board connector for adsp-2106x ez-ice emulator (jumpers in place) the 14-pin, 2-row pin strip header is keyed at the pin 3 location; pin 3 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie and samtec. the btms, btck, btrst and btdi signals are provided so that the test access port can also be used for board-level testing. when the connector is not being used for emulation, place jumpers between the bxxx pins and the xxx pins as shown in figure 6. if you are not going to use the test access port for board testing, tie btrst to gnd and tie or pull up btck to v dd . the trst pin must be asserted after power-up (through btrst on the connector) or held low for proper operation of the ad14060/AD14060L. none of the bxxx pins (pins 5, 7, 9, 11) are connected on the ez-ice probe. the jtag signals are terminated on the ez-ice probe as follows: signal termination tms driven through 22 w resistor (16 m aC3.2 m a driver) tck driven at 10 mhz through 22 w resistor (16 m aC 3.2 m a driver) trst driven by open-drain driver* (pulled up by on-chip 20 k w resistor) tdi driven by 16 m aC3.2 m a driver tdo one ttl load, no termination clkin one ttl load, no termination (optional signal) emu 4.7 k w pull-up resistor, one ttl load (open-drain output from adsp-2106x) * trst is driven low until the ez-ice probe is turned on by the ez-ice software (after the invocation command). figure 7 shows jtag scan path connections for the multi- processor system. connecting clkin to pin 4 of the ez-ice header is optional. the emu lator only uses clkin when directed to pe rform sharc_a tdi tdo tck tms emu trst ez-ice jtag connector tdi tck tms emu trst tdo clkin other jtag controller sharc_b tdi tdo tck tms emu trst sharc_c tdi tdo tck tms emu trst sharc_d tdi tdo tck tms emu trst jtag device (optional) tdi tdo tck tms trst tdi tdo tck tms emu trst adsp-2106x #n optional figure 7. jtag scan path connections for the ad14060/AD14060L
ad14060/AD14060L C13C rev. a system clkin emu 5k v * tdi tdo 5k v * tdi emu tms tck tdo trst clkin * open drain driver or equivalent, i.e., tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo figure 8. jtag clocktree for multiple adsp-2106x systems operations such as starting, stopping and single-stepping mul- tiple adsp-2106xs in a synchronous manner. if you do not need these operations to occur synchronously on the multiple processors, simply tie pin 4 of the ez-ice header to ground. if synchronous multiprocessor operations are needed and clkin is connected, clock skew between the ad14060/AD14060L and the clkin pin on the ez-ice header must be minimal. if the skew is too large, synchronous operations may be off by one cycle between processors. for synchronous multiprocessor operation tck, tms, clkin and emu should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. if tck, tms and clkin are driv- ing a large number of adsp-2106xs (more than eight) in your system, then treat them as a clock tree using multiple drivers to minimize skew. (see figure 8 jtag clock tree and clock distribution in the high frequency design considerations section of the adsp-2106x users manual). if synchronous multiprocessor operations are not needed (i.e., clkin is not connected), just use appropriate parallel termina- tion on tck and tms. tdi, tdo, emu and trst are not critical signals in terms of skew.
C14C rev. a ad14060/AD14060LCspecifications recommended operating conditions b grade k grade parameter min max min max units v dd supply voltage (5 v) 4.75 5.25 4.75 5.25 v supply voltage (3.3 v) 3.15 3.6 3.15 3.6 v t case case operating temperature C40 +100 0 +85 c electrical characteristics (3.3 v, 5 v supply) case test 5 v 3.3 v parameter temp level test condition min typ max min typ max units v ih1 high level input voltage 1 full i @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih2 high level input voltage 2 full i @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il low level input voltage 1, 2 full i @ v dd = min 0.8 0.8 v v oh high level output voltage 3, 4 full i @ v dd = min, i oh = C2.0 ma 4 4.1 2.4 v v ol low level output voltage 3, 4 full i @ v dd = min, i ol = 4.0 ma 4 0.4 0.4 v i ih high level input current 5, 6, 7 full i @ v dd = max, v in = v dd max 10 10 m a i il low level input current 5 full i @ v dd = max, v in = 0 v 10 10 m a i ilp low level input current 6 full i @ v dd = max, v in = 0 v 150 150 m a i ilpx4 low level input current 7 full i @ v dd = max, v in = 0 v 600 600 m a i ozh three-state leakage current 8, 9, 10, 14 full i @ v dd = max, v in = v dd max 10 10 m a i ozl three-state leakage current 8, 11 full i @ v dd = max, v in = 0 v 10 10 m a i ozhp three-state leakage current 11 full i @ v dd = max, v in = v dd max 350 350 m a i ozlc three-state leakage current 12 full i @ v dd = max, v in = 0 v 1.5 1.5 ma i ozla three-state leakage current 13 full i @ v dd = max, v in = 1.5 v (5 v), 2 v (3.3 v) 350 350 m a i ozlar three-state leakage current 10 full i @ v dd = max, v in = 0 v 4.2 4.2 ma i ozls three-state leakage current 9 full i @ v dd = max, v in = 0 v 150 150 m a i ozlsx4 three-state leakage current 14 full i @ v dd = max, v in = 0 v 600 600 m a i ddin supply current (internal) 15 full iv t ck = 25 ns, v dd = max 1.4 3.4 1.0 2.2 a i ddidle supply current (idle) 16 full i v dd = max 800 760 ma c in input capacitance 17, 18 +25 cv 15 15 pf explanation of test levels test level i 100% production tested 19 . ii 100% production tested at +25 c, and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and analysis, and characterization testing on discrete sharcs. v parameter is typical value only. vi all devices are 100% production tested at +25 c; sample tested at temperature extremes. notes 1 applies to input and bidirectional pins: data 47-0 , addr 31-0 , rd , wr , sw , ack, sbts , irq y 2-0 , flagy0, flag1, flagy2, hbg , cs y, dmar1 , dmar2 , br 6-1 , rpba, cpa y, tfs0, tfsy1, rfs0, rfsy1, lyxdat 3-0 , lyxclk, lyxack, eboota, lboota, ebootbcd, lbootbcd, bmsa , bmsbcd , tms, tdi, tck, hbr , dr0, dry1, tclk0, tclky1, rclk0, rclky1. 2 applies to input pins: clkin, reset , trst . 3 applies to output and bidirectional pins: data 47-0 , addr 31-0 , ms 3-0 rd , wr , page, adrclk, sw , ack, flagy0, flag1, flagy2, timexpy, hbg , redy, dmag1 , dmag2 , br 6-1 , cpa y, dto, dty1, tclk0, tclky1, rclk0, rclky1, tfs0, tfsy1, rfs0, rfsy1 lyxdat 3-0 , lyxclk, lyxack, bmsa , bmsbcd , tdo, emu . 4 see output drive currents for typical drive current capabilities. 5 applies to input pins: sbts , irq y 2-0 , hbr , cs y, dmar1 , dmar2 , rpba, eboota, lboota, ebootbcd, lbootbcd, clkin, reset , tck. 6 applies to input pins with internal pull-ups: dr0, dry1, tdi. 7 applies to bussed input pins with internal pull-ups: trst , tms. 8 applies to three-statable pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flagy0, flag1, flagy2, redy, hbg, dmag1 , dmag2 , bmsa , bmsbcd , tdo, emu . (note that ack is pulled up internally with 2 k w during reset in a multiprocessor system, when id 2-0 = 001 and another adsp- 2106x is not requesting bus mastership. hbg and emu are not tested for leakage current.) 9 applies to three-statable pins with internal pull-ups: dty1, tclky1, rclky1. 10 applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k w during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-2106x is not requesting bus mastership.) 11 applies to three-statable pins with internal pull-downs: lyxdat 3-0 , lyxclk, lyxack. 12 applies to cpa y pin. 13 applies to ack pin when keeper latch enabled. 14 applies to bused three-statable pins with internal pull-ups: dt0, tclk0, rclk0. 15 applies to v dd pins. conditions of operation: each processor executing radix-2 fft butterfly with instruction in cache, one data operand fetch ed from each internal memory block, and one dma transfer occurring from/to internal memory at t ck = 25 ns. 16 applies to v dd pins. idle denotes ad14060/AD14060L state during execution of idle instruction. 17 applies to all signal pins. 18 guaranteed but not tested. 19 link and serial ports: all are 100% tested at die level prior to assembly. all are 100% ac tested at module level; link-4 and s erial-0 are also dc tested at the module level. see timing specifications. specifications subject to change without notice.
ad14060/AD14060L C15C rev. a esd sensitivity the ad14060/AD14060L modules are esd (electrostatic discharge) sensitive devices. electro- static charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subjected to high energy electrostatic discharges. the adsp-21060 processors include proprietary esd protection circuitry to dissipate high energy discharges. per method 3015 of mil-std-883, the adsp-21060 processors have been classified as a class 2 device. proper esd precautions are recommended to avoid performance degradation or loss of function- ality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. absolute maximum ratings* supply voltage (5 v) . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v supply voltage (3.3 v) . . . . . . . . . . . . . . . . C0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . 130 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 seconds) . . . . . . . . . . . . . . . . . +280 c *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing specifications general notes this data sheet represents production released specifications for the ad14060 (5 v), and for the AD14060L (3.3 v). the adsp-21060 die components are 100% tested, and the assembled ad14060/AD14060L units are again extensively tested at- speed, and across-temperature. parametric limits were estab- lished from the adsp-21060 characterization followed by further design/analysis of the ad14060/AD14060L package characteristics. the specifications shown are based on a clkin frequency of 40 mhz (t ck = 25 ns). the dt derating allows specifications at other clkin frequencies (within the min-max range of the t ck specification; see clock input below). dt is the difference between the actual clkin period and a clkin period of 25 ns: dt = t ck C 25 ns use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. (o/d) = open drain (a/d) = active drain warning! esd sensitive device
ad14060/AD14060L C16C rev. a 40 mhzC5 v 40 mhzC3.3 v parameter min max min max units clock input timing requirements: t ck clkin period 25 100 25 100 ns t ckl clkin width low 7 8.75 ns t ckh clkin width high 5 5 ns t ckrf clkin rise/fall (0.4 vC2.0 v) 3 3 ns clkin t ckh t ck t ckl figure 9. clock input 5 v 3.3 v parameter min max min max units reset timing requirements: t wrst reset pulsewidth low 1 4t ck 4t ck ns t srst reset setup before clkin high 2 14 + dt/2 t ck 14 + dt/2 t ck ns notes 1 applies after the power-up sequence is complete. at power-up, the processors internal phase-locked loop requires no more than 2000 clkin cycles while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). 2 only required if multiple adsp-2106xs must come out of reset synchronous to clkin with program counters (pc) equal (i.e., for a simd system). not required for multiple adsp-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes its elf after reset. clkin reset t wrst t srst figure 10. reset 5 v 3.3 v parameter min max min max units interrupts timing requirements: t sir irq2-0 setup before clkin high 1 18 + 3dt/4 18 + 3dt/4 ns t hir irq2-0 hold before clkin high 1 11.5 + 3dt/4 11.5 + 3dt/4 ns t ipw irq2-0 pulsewidth 2 2 + t ck 2 + t ck ns notes 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. clkin irq2-0 t ipw t sir t hir figure 11. interrupts
ad14060/AD14060L C17C rev. a 5 v 3.3 v parameter min max min max units timer switching characteristic: t dtex clkin high to timexp 16 16 ns clkin t dtex t dtex timexp figure 12. timer 5 v 3.3 v parameter min max min max units flags timing requirements: t sfi flag2-0 in setup before clkin high 1 8 + 5dt/16 8 + 5dt/16 ns t hfi flag2-0 in hold after clkin high 1 0.5 C 5dt/16 0.5 C 5dt/16 ns t dwrfi flag2-0 in delay after rd / wr low 1 4.5 + 7dt/16 4.5 + 7dt/16 ns t hfiwr flag2-0 in hold after rd / wr deasserted 1 0.5 0.5 ns switching characteristics: t dfo flag2-0 out delay after clkin high 17 17 ns t hfo flag2-0 out hold after clkin high 4 4 ns t dfoe clkin high to flag2-0 out enable 3 3 ns t dfod clkin high to flag2-0 out disable 15 15 ns note 1 flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle. clkin flag2? out flag output t dfo t hfo t dfo t dfod t dfoe clkin rd , wr flag input t sfi t hfi t hfiwr t dwrfi flag2? in figure 13. flags
ad14060/AD14060L C18C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t dad address, delay to data valid 1, 4 17.5 + dt + w 17.5 + dt + w ns t drld rd low to data valid 1 11.5 + 5dt/8 + w 11.5 + 5dt/8 + w ns t hda data hold from address 2 11ns t hdrh data hold from rd high 2 2.5 2.5 ns t daak ack delay from address 3, 4 13.5 + 7dt/8 + w 13.5 + 7dt/8 + w ns t dsak ack delay from rd low 3 7.5 + dt/2 + w 7.5 + dt/2 + w ns switching characteristics: t drha address hold after rd high C0.5 + h C0.5 + h ns t darl address to rd low 4 1.5 + 3dt/8 1.5 + 3dt/8 ns t rw rd pulsewidth 12.5 + 5dt/8 + w 12.5 + 5dt/8 + w ns t rwr rd high to wr , rd , dmagx low 8 + 3dt/8 + hi 8 + 3dt/8 + hi ns t sadadc address setup before adrclk high 4 C0.5 + dt/4 C0.5 + dt/4 ns w = (number of wait states specified in wait register) t ck. hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). notes 1 data delay/setup: user must meet t dad or t drld or synchronous spec t ssdati . 2 data hold: user must meet t hda or t hdrh or synchronous spec t hdati . see system hold time calculation under test conditions for the calculation of hold times given capacitive and dc loads. 3 ack delay/setup: user must meet t dsak or t daak or synchronous specification t sackc . 4 for ms x, sw , bms , the falling edge is referenced. wr, dmag ack data rd address ms x, sw bms t darl t rw t dad t sadadc t daak t hdrh t hda t rwr t drld adrclk (out) t drha t dsak figure 14. memory readbus master memory readbus master use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to clkin. these specifications apply when the ad14060/ AD14060L is the bus master accessing external memory space. these switching characteristics also apply for bus master syn- chronous read/write timing (see synchronous read/write C bus master below). if these timing requirements are met, the syn- chronous read/write timing can be ignored (and vice versa).
ad14060/AD14060L C19C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t daak ack delay from address, selects 1, 2 13.5 + 7dt/8 + w 13.5 + 7dt/8 + w ns t dsak ack delay from wr low 1 7.5 + dt/2 + w 7.5 + dt/2 + w ns switching characteristics: t dawh address, selects to wr deasserted 2 16.5 + 15dt/16 + w 16.5 + 15dt/16 + w ns t dawl address, selects to wr low 2 2.5 + 3dt/8 2.5 + 3dt/8 ns t ww wr pulsewidth 12 + 9dt/16 + w 12 + 9dt/16 + w ns t ddwh data setup before wr high 6.5 + dt/2 + w 6.5 + dt/2 + w ns t dwha address hold after wr deasserted C1 + dt/16 + h C1 + dt/16 + h ns t datrwh data disable after wr deasserted 3 0.5 + dt/16 + h 6.5 + dt/16 + h 0.5 + dt/16 + h 6.5 + dt/16 + h ns t wwr wr high to wr , rd , dmagx low 7.5 + 7dt/16 + h 7.5 + 7dt/16 + h ns t ddwr data disable before wr or rd low 4.5 + 3dt/8 + i 4.5 + 3dt/8 + i ns t wde wr low to data enabled C1.5 + dt/16 C1.5 + dt/16 ns t sadadc address, selects to adrclk high 2 C0.5 + dt/4 C0.5 + dt/4 ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). notes 1 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc . 2 for msx, sw, bms, the falling edge is referenced. 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. rd , dmag ack data wr address ms x , sw bms t dawl t ww t sadadc t daak t wwr t wde adrclk (out) t ddwr t datrwh t dwha t ddwh t dawh t dsak figure 15. memory writebus master memory writebus master use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to clkin. these specifications apply when the ad14060/ AD14060L is the bus master accessing external memory space. these switching characteristics also apply for bus master syn- chronous read/write timing (see synchronous read/writeCbus master). if these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
ad14060/AD14060L C20C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t ssdati data setup before clkin 3 + dt/8 3 + dt/8 ns t hsdati data hold after clkin 4 C dt/8 4 C dt/8 ns t daak ack delay after address, ms x, sw , bms 1, 2 13.5 + 7 dt/8 + w 13.5 + 7 dt/8 + w ns t sackc ack setup before clkin 2 6.5 + dt/4 6.5 + dt/4 ns t hackc ack hold after clkin C0.5 C dt/4 C0.5 C dt/4 ns switching characteristics: t dadro address, ms x, bms , sw delay after clkin 1 8 C dt/8 8 C dt/8 ns t hadro address, ms x, bms , sw hold after clkin C1 C dt/8 C1 C dt/8 ns t dpgc page delay after clkin 9 + dt/8 17 + dt/8 9 + dt/8 17 + dt/8 ns t drdo rd high delay after clkin C2 C dt/8 5 C dt/8 C2 C dt/8 5 C dt/8 ns t dwro wr high delay after clkin C3 C 3dt/16 5 C 3dt/16 C3 C 3dt/16 5 C 3dt/16 ns t drwl rd / wr low delay after clkin 8 + dt/4 13.5 + dt/4 8 + dt/4 13.5 + dt/4 ns t sddato data delay after clkin 20 + 5dt/16 20 + 5dt/16 ns t dattr data disable after clkin 3 0 C dt/8 8 C dt/8 0 C dt/8 8 C dt/8 ns t dadcck adrclk delay after clkin 4 + dt/8 11 + dt/8 4 + dt/8 11 + dt/8 ns t adrck adrclk period t ck t ck ns t adrckh adrclk width high (t ck /2 C 2) (t ck /2 C 2) ns t adrckl adrclk width low (t ck /2 C 2) (t ck /2 C 2) ns w = (number of wait states specified in wait register) t ck . notes 1 for ms x, sw , bms , the falling edge is referenced. 2 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc . 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. synchronous read/writebus master use these specifications for interfacing to external memory systems that require clkinrelative timing or for accessing a slave adsp-2106x (in multiprocessor memory space). these synchronous switching characteristics are also valid during asyn- chronous memory reads and writes (see memory readbus master and memory writebus master). when accessing a slave adsp-2106x, these switching character- istics must meet the slaves timing requirements for synchronous read/writes (see synchronous read/writebus slave). the slave adsp-2106x must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
ad14060/AD14060L C21C rev. a clkin adrclk address sw ack (in) page rd data (out) wr t dadcck t adrck t adrckl t hadro t daak t dpgc t drwl t sackc t hackc t hsdati t ssdati t drdo t dwro t dattr t sddato t drwl data (in) t dadro t adrckh write cycle read cycle figure 16. synchronous read/writebus master
ad14060/AD14060L C22C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t sadri address, sw setup before clkin 15.5 + dt/2 15.5 + dt/2 ns t hadri address, sw hold before clkin 4.5 + dt/2 4.5 + dt/2 ns t srwli rd / wr low setup before clkin 1 9.5 + 5dt/16 9.5 + 5dt/16 ns t hrwli rd / wr low hold after clkin C3.5 C 5dt/16 8 + 7dt/16 C3.5 C 5dt/16 8 + 7dt/16 ns t rwhpi rd / wr pulse high 3 3 ns t sdatwh data setup before wr high 5.5 5.5 ns t hdatwh data hold after wr high 1.5 1.5 ns switching characteristics: t sddato data delay after clkin 20 + 5dt/16 20 + 5dt/16 ns t dattr data disable after clkin 2 0 C dt/8 8 C dt/8 0 C dt/8 8 C dt/8 ns t dackad ack delay after address, sw 3 10 10 ns t acktr ack disable after clkin 3 C1 C dt/8 7 C dt/8 C1 C dt/8 7 C dt/8 ns notes 1 t srwli (min) = 9.5 + 5dt/16 when multiprocessor memory space wait state (mmsws bit in wait register) is disabled; when mmsws is enabl ed, t srwli (min) = 4 + dt/8. 2 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. 3 t dackad is true only if the address and sw inputs have setup times (before clkin) greater than 10.5 + dt/8 and less than 18.5 + 3dt/4. if the address and sw inputs have setup times greater than 19 + 3dt/4, then ack is valid 15 + dt/4 (max) after clkin. a slave that sees an address with an m fiel d match will respond with ack regardless of the state of mmsws or strobes. a slave will three-state ack every cycle with t acktr . synchronous read/writebus slave use these specifications for bus master accesses of a slaves iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. clkin address sw ack rd data (out) wr write access t sadri t hadri t dackad t acktr t rwhpi t hrwli t srwli t sddato t dattr t srwli t hrwli t rwhpi t hdatwh t sdatwh data (in) read access figure 17. synchronous read/writebus slave
ad14060/AD14060L C23C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t hbgrcsv hbg low to rd / wr / cs valid 1 19.5 + 5dt/4 19.5 + 5dt/4 ns t shbri hbr setup before clkin 2 20 + 3dt/4 20 + 3dt/4 ns t hhbri hbr hold before clkin 2 13.5 + 3dt/4 13.5 + 3dt/4 ns t shbgi hbg setup before clkin 13 + dt/2 13 + dt/2 ns t hhbgi hbg hold before clkin high 5.5 + dt/2 5.5 + dt/2 ns t sbri br x, cpa setup before clkin 3 13 + dt/2 13 + dt/2 ns t hbri br x, cpa hold before clkin high 5.5 + dt/2 5.5 + dt/2 ns t srpbai rpba setup before clkin 20 + 3dt/4 20 + 3dt/4 ns t hrpbai rpba hold before clkin 11.5 + 3dt/4 11.5 + 3dt/4 ns switching characteristics: t dhbgo hbg delay after clkin 8 C dt/8 8 C dt/8 ns t hhbgo hbg hold after clkin C2 C dt/8 C2 C dt/8 ns t dbro br x delay after clkin 8 C dt/8 8 C dt/8 ns t hbro br x hold after clkin C2 C dt/8 C2 C dt/8 ns t dcpao cpa low delay after clkin 9 C dt/8 9 C dt/8 ns t trcpa cpa disable after clkin C2 C dt/8 5.5 C dt/8 C2 C dt/8 5.5 C dt/8 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 4 9.5 10.25 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 4 44 + 27dt/16 44 + 27dt/16 ns t ardytr redy (a/d) disable from cs or hbr high 4 11 11 ns notes 1 for first asynchronous access after hbr and cs asserted, addr 31C0 must be a non-mms value 1/2 t ck before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. 2 only required for recognition in the current cycle. 3 cpa assertion must meet the setup to clkin; deassertion does not need to meet the setup to clkin. 4 (o/d) = open drain, (a/d) = active drive. multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-2106xs ( br x) or a host processor ( hbr , hbg ).
ad14060/AD14060L C24C rev. a figure 18. multiprocessor bus request and host bus request clkin hbr hbg (out) br x (out) hbg (in) br x (in) hbr redy (o/d) rd wr cs cs hbg (out) t drdycs t hbgrcsv t trdyhg t srpbai t hrpbai rpba t shbri t hhbri t hhbgo t dhbgo t hbro t dbro t dcpao t trcpa t shbgi t sbri cpa (out) (o/d) cpa (in) (o/d) t hhbgi t hbri redy (a/d) t ardytr o/d = open drain, a/d = active drive hbg will be delayed by n clock cycles when wait states or bus lock are in effect.
ad14060/AD14060L C25C rev. a 5 v 3.3 v parameter min max min max units read cycle timing requirements: t sadrdl address setup/ cs low before rd low 1 0.5 0.5 ns t hadrdh address hold/ cs hold low after rd 0.5 0.5 ns t wrwh rd / wr high width 6 6 ns t drdhrdy rd high delay after redy (o/d) disable 0.5 0.5 ns t drdhrdy rd high delay after redy (a/d) disable 0.5 0.5 ns switching characteristics: t sdatrdy data valid before redy disable from low 1.5 1.5 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 11 11.5 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read 45 + dt 45 + dt ns t hdarwh data disable after rd high 1.5 9 1.5 9.5 ns write cycle timing requirements: t scswrl cs low setup before wr low 0.5 0.5 ns t hcswrh cs low hold after wr high 0.5 0.5 ns t sadwrh address setup before wr high 5.5 5.5 ns t hadwrh address hold after wr high 2.5 2.5 ns t wwrl wr low width 7 7 ns t wrwh rd / wr high width 6 6 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0.5 0.5 ns t sdatwh data setup before wr high 5.5 5.5 ns t hdatwh data hold after wr high 1.5 1.5 ns switching characteristics: t drdywrl redy (o/d) or (a/d) low delay after wr / cs low 11 11.5 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 15 15 ns t srdyck redy (o/d) or (a/d) disable to clkin 1 + 7dt/16 9 + 7dt/16 0 + 7dt/16 8 + 7dt/16 ns note 1 not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr 31C0 must be a non-mms value 1/2 t clk before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. for address bits to be driven during asynchronous host accesses, see table 8.2 of the adsp-2106x sharc users manual . clkin redy (o/d) o/d = open drain, a/d = active drive t srdyck redy (a/d) figure 19a. synchronous redy timing asynchronous read/writehost to ad14060/AD14060L use these specifications for asynchronous host processor accesses of an ad14060/AD14060L, after the host has asserted cs and hbr (low). after hbg is returned by the ad14060/ AD14060L, the host can drive the rd and wr pins to access the ad14060/AD14060Ls internal memory or iop registers. hbr and hbg are assumed low for this timing.
ad14060/AD14060L C26C rev. a t sadrdl redy (o/d) rd t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t sdatrdy read cycle address/ cs data (out) redy (a/d) o/d = open drain, a/d = active drive t sdatwh t hdatwh t wwrl redy (o/d) wr t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy write cycle t sadwrh data (in) address redy (a/d) t scswrl cs t hcswrh figure 19b. asynchronous read/writehost to adsp-2106x
ad14060/AD14060L C27C rev. a 5 v 3.3 v parameter min max min max units timing requirements: t stsck sbts setup before clkin 12 + dt/2 12 + dt/2 ns t htsck sbts hold before clkin 5.5 + dt/2 5.5 + dt/2 ns switching characteristics: t miena address/select enable after clkin C1.5 C dt/8 C1.25 C dt/8 ns t miens strobes enable after clkin 1 C1.5 C dt/8 C1.5 C dt/8 ns t mienhg hbg enable after clkin C1.5 C dt/8 C1.5 C dt/8 ns t mitra address/select disable after clkin 1 C dt/4 1 C dt/4 ns t mitrs strobes disable after clkin 1 2.5 C dt/4 2.5 C dt/4 ns t mitrhg hbg disable after clkin 3 C dt/4 3 C dt/4 ns t daten data enable after clkin 2 9 + 5dt/16 9 + 5dt/16 ns t dattr data disable after clkin 2 0 C dt/8 8 C dt/8 0 C dt/8 8 C dt/8 ns t acken ack enable after clkin 2 7.5 + dt/4 7.5 + dt/4 ns t acktr ack disable after clkin 2 C1 C dt/8 7 C dt/8 C1 C dt/8 7 C dt/8 ns t adcen adrclk enable after clkin C2 C dt/8 C2 C dt/8 ns t adctr adrclk disable after clkin 9 C dt/4 9 C dt/4 ns t mtrhbg memory interface disable before hbg low 3 C1 + dt/8 C1 + dt/8 ns t menhbg memory interface enable after hbg high 3 18.5 + dt 18.5 + dt ns notes 1 strobes = rd , wr , sw , page, dmag . 2 in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 3 memory interface = address, rd , wr , ms x, sw , hbg , page, dmagx , bms (in eprom boot mode). three-state timingbus master, bus slave, hbr , sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin and the sbts pin. this timing is applicable to bus master tran- sition cycles (btc) and host transition cycles (htc) as well as the sbts pin. clkin sbts ack memory interface t menhbg t mtrhbg hbg memory interface = address, rd , wr , ms x, sw , hbg , page, dmag x. bms (in eprom boot mode) t mitra, t mitrs, t mitrhg t stsck t htsck t dattr t daten t acktr t acken t adctr t adcen adrclk data t miena, t miens, t mienhg memory interface figure 20. three-state timing
ad14060/AD14060L C28C rev. a transfer is controlled by addr 31-0 , rd , wr , ms 3-0 , and ack (not dmag ). for paced master mode, the memory readCbus master, memory writeCbus master, and synchronous read/writeCbus master timing specifications for addr 31-0 , rd , wr , ms 3-0 , sw , page, data 47-0 , and ack also apply. 5 v 3.3 v parameter min max min max units timing requirements: t sdrlc dmar x low setup before clkin 1 55ns t sdrhc dmar x high setup before clkin 1 55ns t wdr dmar x width low (nonsynchronous) 6 6 ns t sdatdgl data setup after dmag x low 2 9.5 + 5dt/8 9.5 + 5dt/8 ns t hdatidg data hold after dmag x high 2.5 2.5 ns t datdrh data valid after dmag x high 2 15.5 + 7dt/8 15.5 + 7dt/8 ns t dmarll dmag x low edge to low edge 23 + 7dt/8 23 + 7dt/8 ns t dmarh dmag x width high 6 6 ns switching characteristics: t ddgl dmag x low delay after clkin 9 + dt/4 16 + dt/4 9 + dt/4 16 + dt/4 ns t wdgh dmag x high width 6 + 3dt/8 6 + 3dt/8 ns t wdgl dmag x low width 12 + 5dt/8 12 + 5dt/8 ns t hdgc dmag x high delay after clkin C2 C dt/8 7 C dt/8 C2 C dt/8 7 C dt/8 ns t vdatdgh data valid before dmag x high 3 7.5 + 9dt/16 7.5 + 9dt/16 ns t datrdgh data disable after dmag x high 4 C0.5 8 C0.5 8 ns t dgwrl wr low before dmag x low C0.5 2.5 C0.5 2.5 ns t dgwrh dmag x low before wr high 9.5 + 5dt/8 + w 9.5 + 5dt/8 + w ns t dgwrr wr high before dmag x high 0.5 + dt/16 3.5 + dt/16 0.5 + dt/16 3.5 + dt/16 ns t dgrdl rd low before dmag x low C0.5 2 C0.5 2 ns t drdgh rd low before dmag x high 10.5 + 9dt/16 + w 10.5 + 9dt/16 + w ns t dgrdr rd high before dmag x high C0.5 3.5 C0.5 3.5 ns t dgwr dmag x high to wr , rd , dmag x low 4.5 + 3dt/8 + hi 4.5 + 3dt/8 + hi ns t dadgh address/select valid to dmag x high 16 + dt 16 + dt ns t ddgha address/select hold after dmag x high C1 C1 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). notes 1 only required for recognition in the current cycle. 2 t sdatdgl is the data setup requirement if dmar x is not being used to hold off completion of a write. otherwise, if dmar x low holds off completion of the write, the data can be driven t datdrh after dmar x is brought high. 3 t vdatdgh is valid if dmar x is not being used to hold off completion of a read. if dmar x is used to prolong the read, then t vdatdgh = 7.5 + 9dt/16 + (n t ck ) where n equals the number of extra cycles that the access is prolonged. 4 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for hand- shake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr 31-0 , rd , wr , sw , page, ms 3-0 , ack, and dmag signals. for paced master mode, the data
ad14060/AD14060L C29C rev. a clkin t sdrlc dmar x data (from adsp-2106x to external drive) data (from external drive to adsp-2106x) rd wr t wdr t sdrhc t dmarh t dmarll t hdgc t wdgh t ddgl t wdgl dmag x t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t sdatdgl * ?emory read ?bus master, ?emory write ?bus master,?and ?ynchronous read/write ?bus master timing specifications for addr 31? , rd , wr , sw , ms 3-0 and ack also apply here. (external device to external memory) (external memory to external device) transfers between adsp-2106x internal memory and external device transfers between external device and external memory* (external handshake mode) t ddgha address ms x , sw t dadgh figure 21. dma handshake timing
ad14060/AD14060L C30C rev. a link ports: 1 clk speed operation 5 v 3.3 v parameter min max min max units receive timing requirements: t sldcl data setup before lclk low 3.5 3 ns t hldcl data hold after lclk low 3 3 ns t lclkiw lclk period (1 operation) t ck t ck ns t lclkrwl lclk width low 6 6 ns t lclkrwh lclk width high 5 5 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 29.5 + dt/2 18 + dt/2 29.5 + dt/2 ns t dlalc lack low delay after lclk high 1 C3 13.5 C3 13.5 ns t endlk lack enable from clkin 5 + dt/2 5 + dt/2 ns t tdlk lack disable from clkin 21 + dt/2 21 + dt/2 ns transmit timing requirements: t slach lack setup before lclk high 18 20 ns t hlach lack hold after lclk high C7 C7 ns switching characteristics: t dlclk lclk delay after clkin (1 operation) 16.5 17.5 ns t dldch data delay after lclk high 3.5 3 ns t hldch data hold after lclk high C3 C3 ns t lclktwl lclk width low (t ck /2) C 2 (t ck /2) + 2 (t ck /2) C 1 (t ck /2) + 1.25 ns t lclktwh lclk width high (t ck /2) C 2 (t ck /2) + 2 (t ck /2) C 1.25 (t ck /2) + 1 ns t dlaclk lclk low delay after lack high (t ck /2) + 8.5 (3 t ck /2) + 17.5 (t ck /2) + 8 (3 t ck /2) + 18 ns t endlk ldat, lclk enable after clkin 5 + dt/2 5 + dt/2 ns t tdlk ldat, lclk disable after clkin 21 + dt/2 21 + dt/2 ns link port service request interrupts: 1 and 2 speed operations timing requirements: t slck lack/lclk setup before clkin low 2 10 10 ns t hlck lack/lclk hold after clkin low 2 2.5 2.5 ns notes 1 lack will go low with t dlalc relative to rising edge of lclk after first nibble is received. lack will not go low if the receivers link buffer is not abou t to fill. 2 only required for interrupt recognition in the current cycle.
ad14060/AD14060L C31C rev. a link ports: 2 clk speed operation 5 v 3.3 v parameter min max min max units r eceive timing requirements: t sldcl data setup before lclk low 2.5 2.25 ns t hldcl data hold after lclk low 2.25 2.25 ns t lclkiw lclk period (2 operation) t ck /2 t ck /2 ns t lclkrwl lclk width low 4.5 5 ns t lclkrwh lclk width high 4.25 4 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 29.5 + dt/2 18 + dt/2 30.5 + dt/2 ns t dlalc lack low delay after lclk high 1 6 16.5 6 18.5 ns transmit timing requirements: t slach lack setup before lclk high 19 19 ns t hlach lack hold after lclk high C6.75 C6.5 ns switching characteristics: t dlclk lclk delay after clkin 9 9 ns t dldch data delay after lclk high 3 2.75 ns t hldch data hold after lclk high C2 C2 ns t lclktwl lclk width low (t ck /4) C 1 (t ck /4) + 1 (t ck /4) C 0.75 (t ck /4) + 1.5 ns t lclktwh lclk width high (t ck /4) C 1 (t ck /4) + 1 (t ck /4) C 1.5 (t ck /4) + 1 ns t dlaclk lclk low delay after lack high (t ck /4) + 9 (3 t cl /4) + 17 (t ck /4) + 9 (3 t cl /4) + 17 ns note 1 lack will go low with t dlalc relative to rising edge of lclk after first nibble is received. lack will not go low if the receivers link buffer is not abou t to fill.
ad14060/AD14060L C32C rev. a clkin lclk ldat(3:0) lack lclk 1x or lclk 2x clkin ldat(3:0) lack (in) lclk 1x or lclk 2x ldat(3:0) lack (out) the t slach requirement applies to the rising edge of lclk only for the first nibble transmitted. clkin transmit t dldch t hldch t dlclk t lclktwh t lclktwl t slach t hlach t dlaclk t sldcl t hldcl t lclkrwh t dlahc t dlalc link port enable or three-state takes effect 2 cycles after a write to a link port control register. t endlk t tdlk receive link port enable/three-state delay from instruction t lclkrwl t lclkiw clkin t slck t hlck link port interrupt setup time lclk lack last nibble transmitted first nibble transmitted lclk inactive (high) out in lack goes low only affter the second nibble is received. figure 22. link ports
ad14060/AD14060L C33C rev. a serial ports 5 v 3.3 v parameter min max min max units external clock timing requirements: t sfse tfs/rfs setup before tclk/rclk 1 44ns t hfse tfs/rfs hold after tclk/rclk 1, 2 4.5 4.5 ns t sdre receive data setup before rclk 1 22ns t hdre receive data hold after rclk 1 4.5 4.5 ns t sclkw tclk/rclk width 9.5 9 ns t sclk tclk/rclk period t ck t ck ns internal clock timing requirements: t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 99ns t hfsi tfs/rfs hold after tclk/rclk 1, 2 11ns t sdri receive data setup before rclk 1 44ns t hdri receive data hold after rclk 1 33ns external or internal clock switching characteristics: t dfse rfs delay after rclk (internally generated rfs) 3 14 14 ns t hfse rfs hold after rclk (internally generated rfs) 3 33ns external clock switching characteristics: t dfse tfs delay after tclk (internally generated tfs) 3 14 14 ns t hfse tfs hold after tclk (internally generated tfs) 3 33ns t ddte transmit data delay after tclk 3 17 17 ns t hdte transmit data hold after tclk 3 55ns internal clock switching characteristics: t dfsi tfs delay after tclk (internally generated tfs) 3 55ns t hfsi tfs hold after tclk (internally generated tfs) 3 C1.5 C1.5 ns t ddti transmit data delay after tclk 3 88ns t hdti transmit data hold after tclk 3 00ns t sclkiw tclk/rclk width (sclk/2) C 2 (sclk/2) + 2 (sclk/2) C 2.5 (sclk/2) + 2.5 ns enable and three-state switching characteristics: t ddten data enable from external tclk 3 3.5 4 ns t ddtte data disable from external tclk 3 11.5 11.5 ns t ddtin data enable from internal tclk 3 00ns t ddtti data disable from internal tclk 3 33ns t dclk tclk/rclk delay from clkin 23 + 3dt/8 23 + 3dt/8 ns t dptr sport disable after clkin 18 18 ns external late frame sync switching characteristics: t ddtlfse data delay from late external tfs or 13 13.8 ns external rfs with mce = 1, mfd = 0 4 t ddtenfs data enable from late fs or mce = 1, mfd = 0 4 3.0 3.5 ns to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. notes 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0.5 ns minimum from drive edge. tfs hold after tck for late external tfs is 0.5 ns minimum from drive edge. 3 referenced to drive edge. 4 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs .
ad14060/AD14060L C34C rev. a t hfse/i t sfse/i (see note 2) drive sample drive t ddte/i t ddtenfs t ddtlfse t hdte/i tclk t hfse/i t sfse/i tfs dt drive sample drive t ddte/i t ddtenfs t ddtlfse t hdte/i late external tfs external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs 1st bit 2nd bit (see note 2) figure 23. external late frame sync
ad14060/AD14060L C35C rev. a dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk / rclk tclk (int) tclk / rclk tclk (ext) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hfse t sclkiw data receive?internal clock t sdre data receive?external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hfse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hfsi data transmit?internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hfse data transmit?external clock clkin sport enable and three-state latency is two cycles t dptr sport disable delay from instruction t dclk low to high only tclk (int) rclk (int) tclk, rclk tfs, rfs, dt clkin tfs (ext) t htfsck t stfsck note: applies only to gated serial clock mode with external tfs, as used in the serial port system i/o for mesh multiprocessing. note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. figure 24. serial ports
ad14060/AD14060L C36C rev. a jtag test access port and emulation 5 v 3.3 v parameter min max min max units timing requirements: t tck tck period t ck t ck ns t stap tdi, tms setup before tck high 5 5 ns t htap tdi, tms hold after tck high 6 6 ns t ssys system inputs setup before tck low 1 88ns t hsys system inputs hold after tck low 1 18.5 19 ns t trstw trst pulsewidth 4t ck 4t ck ns switching characteristics: t dtdo tdo delay from tck low 13 13 ns t dsys system outputs delay after tck low 2 20 20 ns notes 1 system inputs = data 47-0 , addr 31-0 , rd , wr , ack, sbts , sw , hbr , hbg , cs , dmar1 , dmar2 , br 6-1 , rpba, irq 2-0 , flag2-0, dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, eboot, lboot, bms , clkin, reset . 2 system outputs = data 47-0 , addr 31-0 , ms 3-0 , rd , wr , ack, page, adrclk, sw , hbg , redy, dmag1 , dmag2 , br 6-1 , cpa , flag 2-0 , timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, bms . tck t stap t tck t htap t dtdo t ssys t hsys t dsys tms tdi tdo system inputs system outputs figure 25. ieee 11499.1 jtag test access port
ad14060/AD14060L C37C rev. a the p ext equation is calculated for each class of pins that can drive: pin # of % type pins switching 3 c 3 f 3 v dd 2 = p ext address 15 50 55 pf 20 mhz 25 v = 0.206 w ms0 10 55 pf 20 mhz 25 v = 0.00 w wr 1C 55 pf 40 mhz 25 v = 0.055 w data 32 50 25 pf 20 mhz 25 v = 0.200 w adrclk 1 C 15 pf 40 mhz 25 v = 0.015 w p ext (5 v) = 0.476 w p ext (3.3 v) = 0.207 w a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + ( i ddin2 5.0 v ) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. also note that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by d v is dependent on the capacitive load, c l , and the load current, i l . this decay time can be approximated by the following equation: t decay = c l d v i l the output disable time, t dis , is the difference between t measured and t decay as shown in figure 27. the time t measured is the interval from when the reference signal switches to when the output voltage decays d v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with d v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time, t ena , is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram (figure 27). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose d v to be the difference between the adsp-2106xs output voltage and the input threshold for the device requiring the hold time. a typical d v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current output drive currents figure 26 shows typical i-v characteristics for the output drivers of the adsp-2106x. the curves represent the current drive capability of the output drivers as a function of output voltage. source current ?ma source voltage ?v 120 100 ?0 0 5 1 2 3 4 40 ?0 ?0 ?0 80 60 0 20 ?00 ?20 ?40 ?60 high level drive (p device) low level drive (n device) figure 26. adsp-2106x typical drive currents (v dd = 5 v) power dissipation total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. inter- nal power dissipation is calculated in the following way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: C the number of output pins that switch during each cycle (o) C the maximum frequency at which they can switch (f) C their load capacitance (c) C their voltage swing (v dd ) and is calculated by: p ext = o c v dd 2 f the load capacitance should include the processors package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: Ca system with one bank of external data memory ram (32-bit) Cfour 128k 8 ram chips are used, each with a load of 10 pf Cexternal data memory writes occur every other cycle, a rate C of 1/(4t ck ), with 50% of the pins switching Cthe instruction cycle rate is 40 mhz (t ck = 25 ns) and C v dd = 5.0 v.
ad14060/AD14060L C38C rev. a (per data line). the hold time will be t decay plus the minimum disable time (i.e., t hdwd for the write cycle). reference signal t dis output starts driving v oh (measured) ? d v v ol (measured) + d v t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t ena t decay figure 27. output enable/disable +1.5v 50pf to output pin i ol i oh figure 28. equivalent device loading for ac measure- ments (includes all fixtures) input or output 1.5v 1.5v figure 29. voltage reference levels for ac measure- ments (except output enable/disable) capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 28). the delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figures 30 and 31 show how output rise time varies with capacitance. figure 32 graphically shows how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see the previous section output disable time under test conditions.) the graphs of figures 30, 31 and 32 may not be linear outside the ranges shown. load capacitance C pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 3.7 1.1 14.7 7.4 fall time rise time rise and fall times C ns (0.5v C 4.5v, 10% C 90%) figure 30. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 5 v) load capacitance C pf 0 0 20 40 60 80 100 120 rise time fall time 140 160 180 200 0.5 0.6 1.0 1.5 2.0 2.5 3.0 3.5 rise and fall times C ns (0.8vC2.0v) 1.6 2.9 figure 31. typical output rise time (0.8 v C2.0 v) vs. load capacitance (v dd = 5 v) load capacitance C pf output delay or hold C ns 5 C1 25 200 50 75 100 125 150 175 4 3 2 1 nominal C0.7 4.5 figure 32. typ ical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 5 v)
ad14060/AD14060L C39C rev. a ad14060/AD14060L assembly recommendations socket information standard sockets and carriers are available for the ad14060/ AD14060L, if needed. socket part number ic53-3084-262 and carrier part number icc-308-1 are available from yamaichi electronics. trim and form the ad14060/AD14060L will be shipped as shown on the final page of the data sheet with untrimmed and unformed leads and with the nonconductive tie bar in place. this avoids disturbance of lead spacing and coplanarity prior to assembly. optimally, the leads should be trimmed, formed and solder-dipped just prior to placement on the board. trim/form can be accomplished with a universal trim/form, customer-designed trim/form, or with the analog devices developed tooling described below. a trim/form tool specific to the ad14060/AD14060L has been developed and is available for use by all parties at: tintronics industries 2122-a metro circle huntsville, al 35801 205-650-0220 contact person: tom rice the package outline and dimensions resulting from this tool are shown below. (alternatively, the package can also be trimmed/ formed for cavity-down placement.) load capacitance C pf 0 2 0 20 40 60 80 100 120 y = 0.0796x + 1.17 y = 0.0467x + 0.55 rise time fall time 140 160 180 200 4 6 8 10 12 14 16 18 rise and fall times C ns (10% C 90%) figure 33. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 3.3 v) load capacitance C pf 0 0 20 40 60 80 100 120 y = 0.0391x + 0.36 y = 0.0305x + 0.24 rise time fall time 140 160 180 200 rise and fall times C ns (0.8v C 2.0v) 1 2 3 4 5 6 7 8 9 figure 34. typical output rise time (0.8 v C2.0 v) vs. load capacitance (v dd = 3.3 v) load capacitance C pf output delay or hold C ns 5 C1 25 200 50 75 100 125 150 175 4 3 2 1 nominal C0.7 4.5 y = 0.0329x - 1.65 figure 35. typ ical output delay or hold vs. load capaci- tance (at maximum case t emperature) (v dd = 3.3 v) 0.170 (4.318) 2.110 (53.59) 2.210 0.010 (56.134 0.254) 0.016 min 0 to 10 mils 0 to 8 detail "a"
ad14060/AD14060L C40C rev. a pcb layout guidelines the drawing below assumes that the trim/form tooling described above is used. these recommendations are provided for user convenience and are recommendations only, based on stan- dard practice. pcb pad footprint geometries and placement are illustrated. note: these drawings are recommended pcb layout guide- lines only, and they assume that the trim/form tooling described above is used. 0.015 (0.381) 0.025 (0.635) 1.9000 (48.26) 4 places 2.060 (52.324) 4 places 2.260 (57.404) 4 places 0.025 (0.635) min 0.025 (0.635) min this is a pc board component footprint, not the package outline.
ad14060/AD14060L C41C rev. a thermal characteristics the ad14060/AD14060L is packaged in a 308-lead ceramic quad flatpack (cqfp). the package is optimized for thermal conduction through the core (base of the package) down to the mounting surface. the ad14060/AD14060L is specified for a case temperature (t case ). design of the mounting surface and attachment material should be such that t case is not exceeded. q jc = 0.36 c/w thermal cross-section the data below, together with the detailed mechanical drawings at the end of the data sheet, allows for constructing simple ther- mal models for further analysis within targeted systems. the top layer of the package, where the die are mounted, is a metal v dd layer. the approximate metal area coverage from the metal planes and routing layers is estimated below. thermal conductivity thermal conductivity material w/cm 8 c ceramic 0.18 kovar 0.14 tungsten 1.78 thermoplastic 0.03 silicon 1.45 metal coverage per layer percent metal layer (1 mil thick) v dd 88 sig2 16 sig3 14 gnd 91 sig4 15 sig5 13 base 95 ceramic layer 28 mils ceramic layer 6 mils ceramic layer 6 mils ceramic layer 10 mils ceramic layer 4 mils ceramic layer 10 mils ceramic layer 10 mils ceramic layer 4 mils ceramic layer 10 mils ceramic layer 4 mils surface kovar lid 0.015 mils kovar seal ring height = 50 mils silicon die 19 mils thermoplastic thickness 5 mils v dd sig2 sig3 gnd sig4 sig5 base
ad14060/AD14060L C42C rev. a mechanical characteristics lid deflection analysis external pressure reduction delta pressure deflection 12 psi 10.0 mil 15 psi 11.9 mil mechanical model the data below, together with the detailed mechanical drawings at the end of the data sheet, allows for construction of simple mechanical models for further analysis within targeted systems. mechanical properties material modulus of elasticity ceramic 26 10 3 kg/mm 2 kovar 14.1 10 3 kg/mm 2 tungsten 35 10 3 kg/mm 2 thermoplastic 279 kg/mm 2 silicon 11 10 3 kg/mm 2 308-lead cqfp pin configuration 78 154 155 231 232 308 1 77 ad14060/AD14060L top view 1.780 0.018 1.810 0.005 1.890 0.005 0.012 ref 4x 0.040 0.002 0.302 0.260 0.250 0.345 0.616 0.633 0.653 4x 0.670 4x 2.050 sq.
ad14060/AD14060L C43C rev. a pin pin pin pin pin pin pin pin pin pin pin pin pin pin no. name no. name no. name no. name no. name no. name no. name 1 wr 45 gnd 89 addr13 133 irq b0 177 lc4dat2 221 gnd 265 gnd 2 rd 46 rfsd1 90 addr12 134 irq b1 178 lc4dat3 222 la3ack 266 data24 3 gnd 47 rclkd1 91 addr11 135 irq b2 179 gnd 223 la3clk 267 data25 4 csa 48 drd1 92 gnd 136 gnd 180 lc3ack 224 la3dat0 268 data26 5 csb 49 tfsd1 93 addr10 137 irq c0 181 lc3clk 225 la3dat1 269 data27 6 csc 50 tclkd1 94 addr9 138 irq c1 182 lc3dat0 226 la3dat2 270 v dd 7 csd 51 dtd1 95 addr8 139 irq c2 183 lc3dat1 227 la3dat3 271 data28 8 gnd 52 v dd 96 v dd 140 irq d0 184 lc3dat2 228 v dd 272 data29 9 hbg 53 hbr 97 addr7 141 irq d1 185 lc3dat3 229 la1ack 273 data30 10 redy 54 dmar1 98 addr6 142 irq d2 186 v dd 230 la1clk 274 data31 11 adrclk 55 dmar2 99 addr5 143 v dd 187 lc1ack 231 la1dat0 275 gnd 12 v dd 56 sbts 100 gnd 144 eboota 188 lc1clk 232 la1dat1 276 data32 13 rfs0 57 bmsa 101 addr4 145 lboota 189 lc1dat0 233 la1dat2 277 data33 14 rclk0 58 bmsbcd 102 addr3 146 ebootbcd 190 lc1dat1 234 la1dat3 278 data34 15 dr0 59 sw 103 addr2 147 lbootbcd 191 lc1dat2 235 gnd 279 data35 16 tfs0 60 gnd 104 v dd 148 gnd 192 lc1dat3 236 data0 280 v dd 17 tclk0 61 ms0 105 addr1 149 reset 193 gnd 237 data1 281 data36 18 dt0 62 ms1 106 addr0 150 rpba 194 lb4ack 238 data2 282 data37 19 gnd 63 ms2 107 flaga0 151 gnd 195 lb4clk 239 data3 283 data38 20 cpaa 64 ms3 108 gnd 152 ld4ack 196 lb4dat0 240 v dd 284 data39 21 cpab 65 v dd 109 flaga2 153 ld4clk 197 lb4dat1 241 data4 285 gnd 22 cpac 66 addr31 110 flagb0 154 ld4dat0 198 lb4dat2 242 data5 286 data40 23 cpad 67 addr30 111 flagb2 155 ld4dat1 199 lb4dat3 243 data6 287 data41 24 v dd 68 addr29 112 flagc0 156 ld4dat2 200 v dd 244 data7 288 clkin 25 rfsa1 69 gnd 113 flagc2 157 ld4dat3 201 lb3ack 245 gnd 289 gnd 26 rclka1 70 addr28 114 flagd0 158 v dd 202 lb3clk 246 data8 290 data42 27 dra1 71 addr27 115 flagd2 159 ld3ack 203 lb3dat0 247 data9 291 data43 28 tfsa1 72 addr26 116 v dd 160 ld3clk 204 lb3dat1 248 data10 292 v dd 29 tclka1 73 v dd 117 flag1 161 ld3dat0 205 lb3dat2 249 data11 293 data44 30 dta1 74 addr25 118 emu 162 ld3dat1 206 lb3dat3 250 v dd 294 data45 31 gnd 75 addr24 119 timexpa 163 ld3dat2 207 gnd 251 data12 295 data46 32 rfsb1 76 addr23 120 timexpb 164 ld3dat3 208 lb1ack 252 data13 296 data47 33 rclkb1 77 addr22 121 timexpc 165 gnd 209 lb1clk 253 data14 297 gnd 34 drb1 78 addr21 122 timexpd 166 ld1ack 210 lb1dat0 254 data15 298 br 1 35 tfsb1 79 addr20 123 gnd 167 ld1clk 211 lb1dat1 255 gnd 299 br 2 36 tclkb1 80 v dd 124 tdo 168 ld1dat0 212 lb1dat2 256 data16 300 br 3 37 dtb1 81 addr19 125 trst 169 ld1dat1 213 lb1dat3 257 data17 301 br 4 38 v dd 82 addr18 126 tdi 170 ld1dat2 214 v dd 258 data18 302 br 5 39 rfsc1 83 addr17 127 tms 171 ld1dat3 215 la4ack 259 data19 303 br 6 40 rclkc1 84 gnd 128 tck 172 v dd 216 la4clk 260 v dd 304 page 41 drc1 85 addr16 129 v dd 173 lc4ack 217 la4dat0 261 data20 305 v dd 42 tfsc1 86 addr15 130 irq a0 174 lc4clk 218 la4dat1 262 data21 306 dmag1 43 tclkc1 87 addr14 131 irq a1 175 lc4dat0 219 la4dat2 263 data22 307 dmag2 44 dtc1 88 v dd 132 irq a2 176 lc4dat1 220 la4dat3 264 data23 308 ack pin configurations
ad14060/AD14060L C44C rev. a c3225C7C10/97 printed in u.s.a. package dimensions dimensions shown in inches and (mm). 308-lead ceramic quad flatpack (cqfp) (qs-308) 1 2.300 6 0.030 (58.42 6 0.762) 77 78 154 155 231 232 308 0.015 (0.381) x 45 3 places 0.008 6 0.002 (0.203 6 0.051) 0.025 (0.635) typ 0.340 6 0.010 (8.636 6 0.254) 4x 2.050 6 0.012 (52.07 6 0.305) 2.730 6 0.015 (69.34 6 0.381) 3.000 6 0.010 (76.2 6 0.254) 3.050 (77.47) max top view 0.040 (1.016) x 45 1.890 6 0.005 (48.006 6 0.127) 0.005 +0.0015 C0.001 (0.127 +0.0381 C0.025) 0.160 (4.064) max 0.035 (0.889) max 0.092 6 0.009 (2.337 6 0.229) ordering guide part number case temperature range smd instruction rate operating voltage ad14060bf-4 C40 c to +100 c n/a 40 mhz 5 v AD14060Lbf-4 C40 c to +100 c n/a 40 mhz 3.3 v 5962-9750601hxc C40 c to +100 c qml-h 40 mhz 5 v 5962-9750701hxc* C40 c to +100 c qml-h 40 mhz 3.3 v *part numbers marked with an * are shipping as x-grade (preproduction) material at the time of this printing. these parts are p ackaged in a 308-lead ceramic quad flatpack package (cqfp). mil-smd parts, in the same package, are in development.

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